In general, a static RAM (Static RAM, hereinafter referred to as SRAM) has a memory cell array wherein memory cells cross-connecting a pair of inverters is arranged in the form of a matrix. In each memory cell, the mutual connecting points of inverter pair are connected with bit line pair via a pair of transfer transistors and the gates of transfer transistor pair are connected with the word lines. The bit line is connected with sense amplifier circuits.
In the read operation of SRAM, the clock signal and address signal are supplied first from an external circuit and the corresponding word line is selected by decoding the address signal in synchronization with the clock signal. When the word line is selected, the corresponding transfer transistor pair is turned ON and thereby the inverter pair of the corresponding memory cells is connected with the bit line pair. The bit line pair is driven with the data stored in the inverter pair of memory cells. A potential difference of driven bit line pair is amplified with a sense amplifier circuit responding to the sense amplifier drive signal and thereby the stored data of memory cells are read out. As a sense amplifier drive signal generating circuit for driving the sense amplifier circuit in the read operation explained above, a generating circuit using the self-timing circuit has been known (for example, refer to the patent document 1).
FIG. 1 is a schematic diagram of a circuit configuration of SRAM provided with the self-timing circuit of the related art.
The existing self-timing circuit 11 comprises at least one dummy memory cell SDMC for self-timing, a dummy word line DWL for selecting dummy memory cells, dummy line pair DBL, XDBL for detecting the data stored in the dummy memory cell, and a timing control circuit 12 for generating the self-timing signal SLF on the basis of the potentials of dummy bit line pair DBL, XDBL. The dummy memory cell SDMC for self-timing includes, like the ordinary memory cell MC in the memory cell array, inverter pair and transfer gate pair.
Moreover, the dummy memory cell SDMC for self-timing is sequentially arranged from the position furthest from the timing control circuit 12 on the dummy bit line pair DBL, XDBL. In view of setting a load resulting from wiring capacitance of the dummy word line DWL and dummy bit line pair DBL, XDBL equal to that of the word line WL and bit line pair BL, XBL within the memory cell array MCA, a plurality of dummy memory cells for load LDMCs are provided respectively to the dummy word line DWL and dummy bit line pair DBL, XDBL.
Operations of the existing self-timing circuit 11 will be explained with reference to FIG. 2. As illustrated in FIG. 2, the dummy word line DWL is selected in synchronization with selection of the predetermined word line WL within the memory cell array MCA. Selection of the dummy word line DWL causes the transfer gate pair of the dummy memory cell SDMC for self-timing to turn ON, and the inverter pair of the dummy memory cell SDMC for self-timing is connected with the dummy bit line pair DBL, XDBL. Thereby, dummy bit line pair DBL, XDBL driven by above process generates the predetermined potential difference.
The timing control circuit 12 detects a potential of any one of the dummy bit line pair DBL, XDBL (XDBL in the figure) and activates the self-timing signal SLF when the potential of the dummy bit line (XDBL) as the detection object becomes smaller than the predetermined value. The self-timing signal SLF is supplied to a control circuit 13 and is then delayed for the specified time with a delay circuit 14 provided within the control circuit 13. The control circuit 13 supplies an output signal of the delay circuit 14 to a sense amplifier circuit 14 as the sense amplifier drive signal SA. The sense amplifier circuit 14 amplifies, responding to the sense amplifier drive signal SA supplied, a potential difference of the selected bit line pair BL, XBL usually driven with the memory cell MC in order to read the data stored.
In this timing, driving capability for the dummy bit line pair DBL, XDBL is adjusted through load adjustment of the dummy memory cell for load LDMC and amount of delay with the delay circuit 14 is also adjusted, in view of adjusting the activation timing of the sense amplifier drive signal SA to the optimum timing.
Here, even if the driving capability of ordinary memory cell MC within the memory cell array MCA is fluctuated due to fluctuation in manufacture, driving capability of the dummy memory cell SDMC is also fluctuated because the manufacturing process is identical. Namely, when driving capability of the ordinary memory cell MC is fluctuated in the direction to become fast, driving capability of the dummy memory cell SDMC also fluctuates in the direction to become fast. In the sense amplifier drive signal generating circuit utilizing the self-timing circuit 11 of FIG. 1, the activation timing of the sense amplifier drive signal SA is determined on the basis of the potential of the dummy bit line pair DBL, XDBL driven with the dummy memory cell SDMC. Accordingly, the activation timing of the sense amplifier drive signal SA can be adjusted automatically to the optimum timing in accordance with fluctuation in manufacture of the driving capability of the ordinary memory cell MC.
Meanwhile, a gate potential is set to always turn off the transfer transistor pair in the dummy memory cell for load LDMC connected to the dummy bit line pair DBL, XDBL. Therefore, the dummy memory cell for load LDMC only adds primarily the wiring capacitance similar to that of the memory array MCA to the dummy bit line pair DBL, XDBL and does not drive the dummy bit line pair DBL, XDBL.
However, in recent years, a semiconductor integrated circuit is more and more developed in its fine structure and therefore it is impossible to neglect a leak current Ileak under the condition that the transfer transistor in the memory cell is turned off. Therefore, the dummy bit line pair DBL, XDBL of the dummy memory cell for load LDMC is driven with the off leak current Ileak in the actual SRAM.
When the dummy bit line (XDBL) as the detection object of the timing control circuit 12 is driven with the off leak currents Ileak not only of the dummy memory cell for self-timing SDMC but also of the dummy memory cell for load LDMC, lowering rate of the potential of the dummy bit line (XDBL) as the detection object becomes fast as much as the drive with the off leak current Ileak. Thereby, activation timing of the self-timing signal SLF becomes faster than the primarily timing. Accordingly, the sense amplifier drive signal SA is also activated faster than the primary timing corresponding to above event. As a result, the data stored in the ordinary memory cell MC is likely read erroneously in the sense amplifier circuit 14.
On the other hand, the dummy bit line of the dummy bit line pair DBL, XDBL which is lowered in the direction to L level with the off leak current Ileak in the dummy memory cell for load LDMC is determined depending on the data stored in the dummy memory cell for load LDMC. The data stored in the dummy memory cell for lad LDMC is determined freely when the power of SRAM is turned on when the connecting node of the inverter pair is in the floating state and is not identified, unlike the dummy memory cell for self-timing SDMC.
Here, the technology is known (for example, refer to the patent document 1), in which the stored data of dummy memory cell for self-timing SDMC and the dummy memory cell for load LDMC connected to the dummy bit line pair DBL, XDBL are set to become the data inverted with each other in the self-timing circuit 11, in order to minimize, considering the process explained above, influence of drive with the off leak current Ileak of the dummy memory cell for load LDMC to the dummy bit line (XDBL) as the detection object of the timing control circuit 12.
FIG. 3 illustrates an example of the setting pattern of the stored data of dummy memory cell for self-timing SDMC and dummy memory cell for load LDMC connected to the dummy bit line pair DBL, XDBL. As illustrated in FIG. 3, potentials of the connecting nodes n1, n2 of the inverter pair INV1, INV2 are set, on the contrary, in the fixed patterns with each other between the dummy memory cell for self-timing SDMC and dummy memory cell for load LDMC.
In the configuration explained above, a potential of the dummy bit line XDBL is lowered to the L level only with the dummy memory cell for self-timing SDMC and meanwhile the dummy bit line DBL is driven with the off leak current of all dummy memory cells for load LDMC. Since the self-timing signal SLF is generated on the basis of the potential of the dummy bit line XDBL, it can be prevented that the activation timing of the sense amplifier drive signal SLF becomes faster than the primary timing due to the influence of drive with the off leak current Ileak.
However, the self-timing circuit 11 illustrated in FIG. 3 also originates a problem, when the SRAM is placed in the higher temperature due to change in ambient temperature, that the off leak current Ileak increases and thereby erroneous read likely occurs in the sense amplifier circuit 14.
FIG. 4 is a diagram for explaining the problem explained above. It is considered here that the data stored in the non-selected memory cell in the bit line pair BL, XBL connected to the selected memory cell is completely inverted from the data stored in the selected memory cell in the memory cell MCA.
As illustrated in FIG. 4, when the off leak current Ileak increases, one bit line (BL, in the figure) is lowered to a large extent in the direction of L level with the inverter pair of the selected memory cell and the other bit line (XBL, in the figure) is also lowered in the direction of L level with the off lead current Ileak of the non-selected memory cell. Accordingly, potential of the bit line XBL is reduced as the time passes. Accordingly, in the case explained above, the timing wherein a potential difference of the bit line pair BL, XBL becomes equal to the predetermined potential difference is delayed most.
On the other hand, in the self-timing circuit 11 illustrated in FIG. 3, the self-timing signal SLF is activated when only the potential of dummy bit line XDBL is detected after the stored data of the dummy memory cells SDMC, LDMC are set to minimize influence of drive with the off leak current Ileak for the dummy bit line XBL as the detection object. Therefore, the activation timing of the self-timing signal SLF is not almost influenced by amplitude of the off leak current Ileak. Namely, the sense amplifier drive signal SA is activated in almost in the same timing without relation to the off leak current Ileak.
Therefore, when the off leak current Ileak increases, the activation timing of the sense amplifier drive signal SA becomes faster than the timing where the predetermined potential difference is generated in the bit line pair BL, XBL and thereby erroneous read of stored data is likely generated. Therefore, a first object of the present invention is to provide a semiconductor memory which can prevent erroneous read of the stored data of the ordinary memory cell MC even when the off leak current Ileak increases.
Moreover, FIG. 5 illustrates an example of layout of the dummy memory cells SDMC, LDMC in the self-timing circuit of the related art of FIG. 1. As illustrated in FIG. 5, the dummy memory cell of the related art is formed in the layout including a unit of the part formed of the inverter pair and transfer transistor pair.
The dummy memory cell of the related art is formed in the layout that the ordinary layout unit 51 formed of the inverters 53, 54 and transfer transistor pair 57 and the symmetrical layout unit 52 formed of the inverters 55, 56 and transfer transistor pair 58 related in the point symmetry or line symmetry to above ordinary layout unit 51 are alternately allocated along the dummy bit line pair DBL, XDBL.
As the dummy memory cell for self-timing SDMC, a plurality of dummy memory cells, for example, are sequentially designated from the furthest position of the timing control circuit 12 on the dummy bit line. In FIG. 5, the gates of the transfer transistor pair 57, 58 of the dummy memory cell for self-timing SDMC1, 2 are connected to the common dummy word, line DWL not illustrated and the gates of the transfer transistor pair of the dummy memory cells for lead LDMC1, 2 are connected to the ground VSS.
In FIG. 5, the write region indicates impurity diffusing layer on a semiconductor wafer and the hatched region indicates gate polysilicon layer formed on the semiconductor wafer. The broken line indicates a local wiring within the memory cell and a thick line indicates a dummy bit line pair DBL, XDBL. A circular mark indicates a contact with the dummy bit line. Moreover, as is understood from FIG. 5, layouts of two inverters forming an inverter pair are not in the line-symmetrical relationship.
Here, an example of layout of the dummy memory cell of FIG. 5 includes a problem that erroneous read of the data stored in the memory cell MC is likely generated when positional displacement is generated between the impurity diffusing layer and gate polysilicon layer in the photoetching process or the like in the manufacturing process.
As is illustrated in FIG. 6, the actual finished area includes the round area at the corners of the impurity diffusing layer and gate polysilicon layer. Therefore, if positional displacement occurs as explained above, for example when the gate polysilicon layer is deviated totally in the left lower direction (refer to FIG. 6) for the impurity diffusing layer, a certain difference is generated in the driving capability of each inverter forming an inverter pair in the ordinary layout unit 51 and symmetrical layout unit 52.
In more detail, inverter characteristics change as explained below due to the positional displacement in the left lower direction in the ordinary layout unit 51. Namely, in the inverter 54 located in the left side, channel length becomes short in the upper side transistor, while in the transistor located in the lower side, channel length becomes long, resulting in narrower channel width. However, in the inverter 53 located in the right side, channel length becomes long in the upper side transistor and channel width becomes wide in the lower side transistor.
On the other hand, in the symmetrical layout unit 52, inverter characteristics change as explained below due to the displacement in the left lower direction. Namely, in the inverter 56 located in the left side, channel width becomes narrow in the upper side transistor and channel length becomes short in the lower side transistor. Meanwhile, in the inverter 55 located in the right side, channel length becomes short in the upper side transistor and channel width becomes wide, while in the lower side transistor, channel length becomes long.
As explained above, driving capability is different with each other among the four inverters 53 to 56 forming the inverter pair of the ordinary layout unit 51 and symmetrical layout unit 52. As a result, a certain difference is generated in the driving capability, in accordance with the positional displacement, between the dummy memory cell SDMC1 including the ordinary layout unit 51 and the dummy memory cell SDMC2 including the symmetrical layout unit 52.
Corresponding to such difference, driving capability for the dummy bit line XDBL as the detection object of the timing control circuit 12 also changes in accordance with positional displacement. Accordingly, activation timing of the self-timing signal SLF changes in accordance with positional displacement and it likely becomes faster than the primary timing.
On the other hand, the memory cell MC in the memory cell array MCA has the layout similar to the layout example of the dummy memory cells SDMC, LDMC in FIG. 5 for each bit line pair BL, XBL. Therefore, when positional displacement occurs and the memory cell MC selected during the read operation includes the layout unit having smaller driving capability among the ordinary layout unit 51 and symmetrical layout unit 52, the timing for generating the predetermined potential difference in the bit line pair BL, XBL likely becomes slower than the primary timing.
Therefore, the activation timing of the sense amplifier drive signal SA becomes faster, in accordance with the positional displacement, than the timing for generating the predetermined potential difference in the bit line pair BL, XBL and thereby erroneous read of stored data is likely generated. Accordingly, the second object of the present invention is to provide a semiconductor memory to prevent erroneous read of the data stored in the ordinary memory cell MC even when the interlayer positional displacement occurs in the manufacturing processes.
As explained above, the principal object of the present invention is to provide a semiconductor memory which can surely prevent erroneous read of the data stored in the ordinary memory cell MC without relation to various factors for changing device characteristics such as temperature change and fluctuation in manufacturing processes.
(Patent document 1)
JP-A No. 2003-36678